Nonvolatile semiconductor memory device and method for manufacturing the same

ABSTRACT

A nonvolatile semiconductor memory device, includes: a stacked body including a plurality of insulating films alternately stacked with a plurality of electrode films, the electrode films being divided to form a plurality of control gate electrodes aligned in a first direction; a plurality of semiconductor pillars aligned in a stacking direction of the stacked body, the semiconductor pillars being arranged in a matrix configuration along the first direction and a second direction intersecting the first direction to pierce the control gate electrodes; and a connection member connecting a lower end portion of one of the semiconductor pillars to a lower end portion of one other of the semiconductor pillars, an upper end portion of the one of the semiconductor pillars being connected to a source line, an upper end portion of the one other of the semiconductor pillars being connected to a bit line. At least some of the control gate electrodes are pierced by two of the semiconductor pillars adjacent to each other in the second direction. Two of the semiconductor pillars being connected to each other by the connection member pierce mutually different control gate electrodes.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromthe prior Japanese Patent Application No. 2009-032988, filed on Feb. 16,2009; the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a nonvolatile semiconductor memory deviceincluding multiple insulating films alternately stacked with multipleelectrode films and a method for manufacturing the same.

2. Background Art

Semiconductor memory devices of flash memory and the like conventionallyare constructed by two-dimensionally integrating memory cells on thesurface of a silicon substrate. In such a semiconductor memory device,it is necessary to increase the integration of memory cells to reducethe cost per bit and increase the storage capacity. However, such highintegration in recent years has become difficult in regard to both costand technology.

Methods of three-dimensional integration by stacking memory cells havebeen proposed as technology to breakthrough the limitations ofincreasing the integration. However, methods that simply stack andpattern one layer after another undesirably increase the number of stepsas the number of stacks increases, and the costs undesirably increase.In particular, the increase of lithography steps for patterning thetransistor structure is a main cause of increasing costs. Therefore, thereduction of the chip surface area per bit by stacking has not led tolower costs per bit as much as downsizing within the chip plane and isproblematic as a method for increasing the storage capacity.

In consideration of such problems, the inventors have proposed acollectively patterned three-dimensional stacked memory (for example,refer to JP-A 2007-266143 (Kokai)). In such technology, selectiontransistors including silicon pillars aligned in the vertical directionas channels are formed on a silicon substrate and a stacked body isformed thereupon by alternately stacking electrode films and insulativefilms and subsequently making through-holes in the stacked body bycollective patterning. A charge storage layer is formed on a side faceof each through-hole, and silicon pillars are newly buried in theinteriors of through-holes to connect to the silicon pillars of theselection transistors. A memory transistor is thereby formed at anintersection between each electrode film and the silicon pillar. Then,selection transistors are further formed thereupon.

In such a collectively patterned three-dimensional stacked memory, acharge can be removed from and put into the charge storage layer fromthe silicon pillar to store information by controlling an electricalpotential of each electrode film and each silicon pillar. According tosuch technology, the through-holes are made by collectively patterningthe stacked body. Therefore, the number of lithography steps does notincrease and cost increases can be suppressed even in the case where thenumber of stacks of the electrode films increases.

However, to construct such a collectively patterned three dimensionalstacked memory, it is necessary to remove silicon oxide of native oxidefilms and the like from the bottom faces of the through-holes whenburying silicon pillars in the interiors of the through-holes made inthe stacked body to provide good electrical contact between the siliconpillars forming the channels of the selection transistors and the newlyburied silicon pillars. Normally, pre-processing is performed using ahydrofluoric acid-based solution prior to burying the silicon pillars inthe through-holes. However, such pre-processing damages the chargestorage layer and undesirably causes deterioration of the memorytransistor characteristics.

SUMMARY OF THE INVENTION

According to an aspect of the invention, there is provided a nonvolatilesemiconductor memory device, including: a stacked body including aplurality of insulating films alternately stacked with a plurality ofelectrode films, the electrode films being divided to form a pluralityof control gate electrodes aligned in a first direction; a plurality ofselection gate electrodes provided on the stacked body and aligned inthe first direction; a plurality of semiconductor pillars aligned in astacking direction of the stacked body, the semiconductor pillars beingarranged in a matrix configuration along the first direction and asecond direction intersecting the first direction to pierce the controlgate electrodes and the selection gate electrodes; a plurality of sourcelines aligned in the first direction and connected to upper end portionsof some of the semiconductor pillars; a plurality of bit lines alignedin the second direction and connected to upper end portions of aremainder of the semiconductor pillars; a connection member connecting alower end portion of one of the semiconductor pillars to a lower endportion of one other of the semiconductor pillars, an upper end portionof the one of the semiconductor pillars being connected to the sourceline, an upper end portion of the one other of the semiconductor pillarsbeing connected to the bit line; a charge storage layer provided betweenone of the control gate electrode and one of the semiconductor pillar;and a gate insulating film provided between one of the selection gateelectrode and one of the semiconductor pillar, at least some of thecontrol gate electrodes being pierced by two of the semiconductorpillars adjacent to each other in the second direction, two of thesemiconductor pillars being connected to each other by the connectionmember and provided to pierce mutually different control gateelectrodes.

According to another aspect of the invention, there is provided a methodfor manufacturing a nonvolatile semiconductor memory device, including:forming a conducting film on a substrate; making a plurality of recessesin an upper face of the conducting film, the recesses being arranged ina matrix configuration along a first direction and a second directionintersecting the first direction; filling sacrificial members into therecesses; forming a stacked body on the conducting film, the stackedbody including a plurality of insulating films alternately stacked witha plurality of electrode films; making through-holes in the stackedbody, the through-holes being aligned in a stacking direction of thestacked body and provided in a matrix configuration along the firstdirection and the second direction, two of the through-holes adjacent inthe second direction reaching each of the sacrificial members;performing etching via the through-holes to remove the sacrificialmembers; forming a charge storage layer on inner faces of thethrough-holes and the recesses; filling a semiconductor material intointeriors of the through-holes and the recesses to form a connectionmember in the recesses and semiconductor pillars in the through-holes;making a trench in the stacked body to divide the electrode films into aplurality of control gate electrodes aligned in the first direction, thetrench being aligned in the first direction to link regions between thetwo semiconductor pillars connected to each other by the connectionmember, the control gate electrodes being pierced by two of thesemiconductor pillars arranged along the second direction; forminganother conducting film on the stacked body; making other through-holesin the another conducting film in regions directly above thethrough-holes; forming a gate insulating film on inner faces of theother through-holes; filling a semiconductor material into interiors ofthe other through-holes to form other semiconductor pillars connected tothe semiconductor pillars; dividing the another conducting film to forma plurality of selection gate electrodes aligned in the first direction;forming a plurality of source lines aligned in the first direction andconnected to upper end portions of some of the other semiconductorpillars; and forming a plurality of bit lines aligned in the seconddirection and connected to upper end portions of a remainder of theother semiconductor pillars.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a perspective view illustrating a nonvolatile semiconductormemory device according to a first embodiment of the invention;

FIG. 2 is a cross-sectional view illustrating the nonvolatilesemiconductor memory device according to the first embodiment;

FIG. 3 is a circuit diagram illustrating the nonvolatile semiconductormemory device according to the first embodiment;

FIG. 4 is another cross-sectional view illustrating the nonvolatilesemiconductor memory device according to the first embodiment;

FIG. 5 is a plan view illustrating the nonvolatile semiconductor memorydevice according to the first embodiment;

FIG. 6 illustrates potentials applied to each of the electrodes andinterconnects during the operations of the nonvolatile semiconductormemory device according to the first embodiment;

FIGS. 7 to 15 are cross-sectional views of steps, illustrating a methodfor manufacturing the nonvolatile semiconductor memory device accordingto the first embodiment;

FIGS. 16A and 16B are cross-sectional views of steps, illustratingportions of a stacked body divided in the step illustrated in FIG. 13;

FIG. 17 is a cross-sectional view illustrating a nonvolatilesemiconductor memory device according to a second embodiment of theinvention;

FIG. 18 is a plan view illustrating the nonvolatile semiconductor memorydevice according to the second embodiment;

FIG. 19 is a cross-sectional view illustrating a nonvolatilesemiconductor memory device according to a modification of the secondembodiment;

FIG. 20 is a plan view illustrating the nonvolatile semiconductor memorydevice according to the modification of the second embodiment;

FIG. 21 is a cross-sectional view illustrating a nonvolatilesemiconductor memory device according to a third embodiment of theinvention; and

FIG. 22 is a plan view illustrating the nonvolatile semiconductor memorydevice according to the third embodiment.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments of the invention will now be described with reference to thedrawings.

First, a first embodiment of the invention will be described.

FIG. 1 is a perspective view illustrating a nonvolatile semiconductormemory device according to this embodiment.

FIG. 2 is a cross-sectional view illustrating the nonvolatilesemiconductor memory device according to this embodiment.

FIG. 3 is a circuit diagram illustrating the nonvolatile semiconductormemory device according to this embodiment.

FIG. 4 is another cross-sectional view illustrating the nonvolatilesemiconductor memory device according to this embodiment.

FIG. 5 is a plan view illustrating the nonvolatile semiconductor memorydevice according to this embodiment.

Although FIG. 4 illustrates an example in which twenty-four layers ofcontrol gate electrodes are provided, FIG. 1 to FIG. 3 illustrate onlyfour layers of control gate electrodes for easier viewing of thedrawings. For easier viewing of the drawings in FIG. 1, FIG. 4, and FIG.5, only a silicon substrate and electrically conducting portions areillustrated, and insulating portions are omitted. In particular, FIG. 5illustrates only the silicon substrate, back gates, the control gateelectrodes, and U-shaped silicon members. FIG. 3 illustrates one pair ofmemory strings sharing the control gate electrodes.

Features of the nonvolatile semiconductor memory device according tothis embodiment include providing a collectively patterned threedimensional stacked memory device in which memory transistors areprovided at intersections between silicon pillars and control gateelectrodes by forming one pair of silicon pillars in a U-shaped pillarconfiguration, piercing each of the control gate electrodes with twoseries of silicon pillars, providing the pair of silicon pillars havingthe U-shaped pillar configuration to pierce mutually different controlgate electrodes, dividing the memory cell formation region into multipleblocks, and therefore providing appropriate termination at block endportions and between blocks. Details of the configuration of such anonvolatile semiconductor memory device will now be described.

A nonvolatile semiconductor memory device 1 (hereinbelow also simplyreferred to as “device 1”) according to this embodiment illustrated inFIG. 1 and FIG. 2 includes a silicon substrate 11. A memory cellformation region in which memory cells are formed and a peripheralcircuit region (not illustrated) in which peripheral circuits are formedare set in the silicon substrate 11. The peripheral circuit region isdisposed around the memory cell formation region.

An insulating film 10 is provided on the silicon substrate 11 in thememory cell formation region. A conducting film, e.g., a polysiliconfilm 12, is formed thereupon to form a back gate BG. Multiple electrodefilms 14 are alternately stacked with multiple insulating films 15 onthe back gate BG. The multiple electrode films 14 and the multipleinsulating films 15 form a stacked body ML.

An XYZ orthogonal coordinate system will now be introduced forconvenience of description in the specification. In this coordinatesystem, two mutually orthogonal directions parallel to an upper face ofthe silicon substrate 11 are taken as an X direction and a Y direction.A direction orthogonal to both the X direction and the Y direction, thatis, the stacking direction of the layers, is taken as a Z direction.

The electrode films 14 are formed of, for example, polysilicon. In thecentral portion of the stacked body ML in the X direction, the electrodefilms 14 are divided along the Y direction to form multiple control gateelectrodes CG aligned in the X direction. Each layer of the electrodefilms 14 is patterned to have the same pattern as viewed from above,i.e., the Z direction. As described below, the electrode films 14 arenot divided along the Y direction at both X-direction end portions ofthe stacked body ML to form a pair of comb-shaped configurations. On theother hand, the insulating films 15 are made of, for example, siliconoxide (SiO₂) and function as inter-layer insulating films to insulatethe electrode films 14 from each other.

An insulating film 16, a conducting film 17, and an insulating film 18are formed in this order on the stacked body ML. The conducting film 17is made of, for example, polysilicon and is divided along the Ydirection to form multiple selection gate electrodes SG aligned in the Xdirection. Two of the selection gate electrodes SG are provided in theregion directly above each of the control gate electrodes CG of theuppermost layer. In other words, the selection gate electrodes SG arealigned in the same direction (the X direction) as the control gateelectrodes CG but with half the arrangement period. As described below,the selection gate electrodes SG include selection gate electrodes SGbon the bit line side and selection gate electrodes SGs on the sourceline side.

An insulating film 19 is provided on the insulating film 18. Sourcelines SL are provided on the insulating film 19 to align in the Xdirection. The source lines SL are disposed in the region directly aboveevery other one of the control gate electrodes CG of the uppermost layerarranged along the Y direction. An insulating film 20 is provided on theinsulating film 19 to cover the source lines SL. Multiple bit lines BLare provided on the insulating film 20 to align in the Y direction. Thesource lines SL and the bit lines BL may be formed from metal films.

Multiple through-holes 21 are made to pierce the stacked body ML andalign in the stacking direction (the Z direction) of the layers. Each ofthe through-holes 21 pierces each level of the control gate electrodesCG such that the lower end reaches the back gate BG. The through-holes21 are arranged in a matrix configuration along the X direction and theY direction. Because the control gate electrodes CG are aligned in the Xdirection, the through-holes 21 arranged in the X direction pierce thesame control gate electrodes CG. The arrangement period of thethrough-holes 21 in the Y direction is half of the arrangement period ofthe control gate electrodes CG. Thereby, two of the through-holes 21arranged in the Y direction form one set, and the through-holes 21 ofthe same set pierce the same control gate electrodes CG.

A communicating hole 22 is made in the upper layer portion of the backgate BG to communicate from the lower end portion of one through-hole 21to the lower end portion of another through-hole 21 positioned oneseries away from the one through-hole 21 in the Y direction as viewedfrom the one through-hole 21. Thereby, one continuous U-shaped hole 23is made by one pair of through-holes 21 adjacent in the Y direction andthe communicating hole 22 that communicates between the pair. MultipleU-shaped holes 23 are made in the stacked body ML.

An ONO film (Oxide Nitride Oxide film) 24 is provided on the inner faceof the U-shaped hole 23. The ONO film 24 includes an insulative blocklayer 25, a charge storage layer 26, and an insulative tunneling layer27 stacked in this order from the outside. The block layer 25 contactsthe back gate BG, the control gate electrodes CG, and the insulatingfilms 15. The block layer 25 and the tunneling layer 27 are made of, forexample, silicon oxide. The charge storage layer 26 is made of, forexample, silicon nitride.

A semiconductor material, e.g., polysilicon, doped with an impurity isfilled into the interior of the U-shaped hole 23. Thereby, a U-shapedsilicon member 33 is provided in the interior of the U-shaped hole 23.The portions of the U-shaped silicon member 33 positioned in thethrough-holes 21 form silicon pillars 31, and the portion of theU-shaped silicon member 33 positioned in the communicating hole 22 formsa connection member 32. The silicon pillars 31 have columnarconfigurations aligned in the Z direction and are, for example, circularcolumns. The connection member 32 has a columnar configuration alignedin the Y direction and is, for example, a rectangular column. The twosilicon pillars 31 and the one connection member 32 forming the U-shapedsilicon member 33 are formed integrally. Accordingly, the U-shapedsilicon member 33 is formed continuously without breaks along thelongitudinal direction thereof. The U-shaped silicon member 33 isinsulated from the back gate BG and the control gate electrodes CG bythe ONO film 24.

Multiple through-holes 51 are made in the insulating film 16, theselection gate electrodes SG, and the insulating film 18. Each of thethrough-holes 51 is made in a region directly above the through-hole 21to communicate with the through-hole 21. Here, because the selectiongate electrodes SG are aligned in the X direction, the through-holes 51arranged in the X direction pierce the same selection gate electrode SG.The arrangement period of the through-holes 51 in the Y direction is thesame as the arrangement period of the selection gate electrodes SG, andthe phase of the arrangement also is the same. Accordingly, the multiplethrough-holes 51 arranged in the Y direction correspond to the selectiongate electrodes SG on a one-to-one basis and pierce mutually differentselection gate electrodes SG.

A gate insulating film 28 is formed on the inner face of thethrough-hole 51. Polysilicon, for example, is filled into the interiorof the through-hole 51 to form a silicon pillar 34. The silicon pillar34 has a columnar configuration aligned in the Z direction and is, forexample, a circular column. The lower end portion of the silicon pillar34 connects to the upper end portion of the silicon pillar 31 formed inthe region directly below. The silicon pillar 34 is insulated from theselection gate electrode SG by the gate insulating film 28. The U-shapedsilicon member 33 and one pair of silicon pillars 34 connected to theupper end portions thereof form a U-shaped pillar 30.

The positional relationship of the U-shaped pillar 30 with the controlgate electrodes CG, the selection gate electrodes SG, the source linesSL, and the bit lines BL will now be described.

The U-shaped pillar 30 is formed of one pair of silicon pillars 34 and31 adjacent in the Y direction and connected to each other by theconnection member 32. On the other hand, the control gate electrodes CG,the selection gate electrodes SG, and the source lines SL are aligned inthe X direction; and the bit lines BL are aligned in the Y direction.Although the arrangement period in the Y direction of the U-shapedpillars 30 and the control gate electrodes CG are the same, the phasesare shifted half a period. Therefore, the pair of silicon pillars 31 ofeach of the U-shaped pillars 30, i.e., the two silicon pillars 31connected to each other by the connection member 32, pierce mutuallydifferent control gate electrodes CG. On the other hand, the two siliconpillars 31 adjacent in the Y direction and belonging to two U-shapedpillars 30 adjacent in the Y direction pierce common control gateelectrodes CG.

The multiple silicon pillars 34 arranged in the Y direction piercemutually different selection gate electrodes SG. Accordingly, the pairof silicon pillars 34 of each of the U-shaped pillars 30 also piercesmutually different selection gate electrodes SG. On the other hand, themultiple U-shaped pillars 30 arranged in the X direction pierce a commonpair of selection gate electrodes SG.

Of the pair of silicon pillars 34 of each of the U-shaped pillars 30,one silicon pillar 34 is connected to the source line SL via a sourceplug SP buried in the insulating film 19. The other silicon pillar 34 isconnected to the bit line BL via a bit plug BP buried in the insulatingfilms 19 and 20. Accordingly, the U-shaped pillar 30 is connectedbetween the bit line BL and the source line SL. In FIG. 1 to FIG. 4, theselection gate electrode SG disposed on the bit line side and pierced bythe U-shaped pillar 30 is labeled as the selection gate electrode SGb.The selection gate electrode SG disposed on the source line side andpierced by the U-shaped pillar 30 is labeled as the selection gateelectrode SGs. The U-shaped pillars 30 arranged in the X directionconnect to a common source line and mutually different bit lines BL.Here the arrangement period of the U-shaped pillars 30 in the Xdirection is the same as the arrangement period of the bit lines BL.Therefore, in the X direction, the U-shaped pillars 30 correspond to thebit lines BL on a one-to-one basis. On the other hand, two of theU-shaped pillars 30 arranged in the Y direction connect as a set to eachof the source lines SL and a common bit line BL.

In the device 1 illustrated in FIG. 1 to FIG. 3, the silicon pillars 31function as channels and the control gate electrodes CG function as gateelectrodes to form vertical memory transistors 35 at the intersectionsbetween the silicon pillars 31 and the control gate electrodes CG. Eachof the memory transistors 35 functions as a memory cell by storingelectrons in the charge storage layer 26 disposed between the siliconpillar 31 and the control gate electrode CG. Because multiple siliconpillars 31 are arranged in a matrix configuration along the X directionand the Y direction in the stacked body ML, the multiple memorytransistors 35 are arranged three dimensionally along the X direction,the Y direction, and the Z direction.

A selection transistor 36 is formed at the intersection between thesilicon pillar 34 and the selection gate electrode SG and includes thesilicon pillar 34 as a channel, the selection gate electrode SG as agate electrode, and the gate insulating film 28 as a gate insulatingfilm. The selection transistor 36 also is a vertical transistor similarto the memory transistor 35 described above.

Because the ONO film 24 is disposed between the connection member 32 andthe back gate BG, a back gate transistor 37 is formed and includes theconnection member 32 as a channel, the back gate BG as a gate electrode,and the ONO film 24 as a gate insulating film. That is, the back gate BGfunctions as an electrode to control the conducting state of theconnection member 32 by an electric field.

As a result, as illustrated in FIG. 3, a memory string 38 is formedalong each of the U-shaped pillars 30 and is connected between the bitline BL and the source line SL. The selection transistor 36 is providedon both end portions of the memory string 38; the back gate transistor37 is provided at the central portion of the memory string 38; and thesame number of memory transistors 35 as electrode film 14 layers areconnected in series between the back gate transistor 37 and each of theselection transistors 36. In other words, the multiple memorytransistors 35 arranged three dimensionally in the stacked body ML arecollected as the memory string 38 for each of the U-shaped siliconmembers 33.

The memory cell formation region of the device 1 illustrated in FIG. 4and FIG. 5 is divided into multiple blocks 50. The positionalrelationship of the blocks 50 and each of the electrically conductivemembers will now be described.

As illustrated in FIG. 4 and FIG. 5, the multiple blocks 50 set in thememory cell formation region are arranged along the Y direction. Theelectrically conductive members of the device 1 aligned in the Xdirection, i.e., the control gate electrodes CG and the selection gateelectrodes SG, and the U-shaped pillars 30 aligned in the Z directionare organized for each block 50. The back gate BG formed along the XYplane is subdivided and electrically mutually separated for each block50. On the other hand, the bit lines BL aligned in the Y direction arealigned to pass through all of the blocks 50 and are shared by all ofthe blocks 50. An element separation film 59 is formed in the region ofthe silicon substrate 11 between the blocks 50.

The control gate electrodes CG of each of the blocks 50 are furtherorganized into two groups. Namely, the control gate electrodes CG aredivided into the control gate electrodes CG disposed in regions directlybelow the source lines SL and pierced by the silicon pillars havingupper end portions connected to the source lines SL (labeled as “controlgate electrodes CGs” in FIG. 4 and FIG. 5) and the control gateelectrodes CG disposed in the regions other than the regions directlybelow the source lines SL and pierced by the silicon pillars havingupper end portions connected to the bit lines BL (labeled as “controlgate electrodes CGb” in FIG. 4 and FIG. 5). The control gate electrodesCGs are alternately arranged with the control gate electrodes CGb alongthe Y direction; the control gate electrodes CGs have common connectionsto each other; and the control gate electrodes CGb have commonconnections to each other. The control gate electrodes CGs and thecontrol gate electrodes CGb are electrically separated.

Specifically, as illustrated in FIG. 4 and FIG. 5, the electrode films14 (referring to FIG. 1) are not divided along the Y direction at bothof the X-direction end portions of the stacked body ML; and incisionsaligned in the Y direction are made intermittently. Thereby, in each ofthe blocks 50, the electrode films 14 are subdivided into a pair ofmutually meshed comb-shaped patterns to form the control gate electrodesCGs and the control gate electrodes CGb, respectively. Although thecontrol gate electrode CGs has three comb teeth and the control gateelectrode CGb has two comb teeth in FIG. 5 to simplify the drawing, thisembodiment is not limited thereto, and the number of comb teeth may behigher.

The lower end portions of the silicon pillars 31 disposed at theY-direction end portions of each of the blocks 50 are not connected tothe connection members 32. Therefore, such silicon pillars 31 do notform memory strings 38 but form dummy silicon pillars 31 d (hereinbelowalso referred to as “dummy pillars”) and do not contribute to storingdata. In the region directly below the dummy pillars 31 d, the back gateBG is not provided, and the element separation film 59 is formed in thesilicon substrate 11.

Operations of the nonvolatile semiconductor memory device 1 according tothis embodiment having the configuration described above will now bedescribed.

FIG. 6 illustrates the potentials applied to each of the electrodes andinterconnects during the operations of the nonvolatile semiconductormemory device 1 according to this embodiment.

In the description hereinbelow, the memory transistor 35 is taken to bean n-channel field effect transistor. The state of the memory transistor35 in which electrons are stored in the charge storage layer 26 and thethreshold shifts to positive is taken as the value “0;” and the state inwhich electrons are not stored in the charge storage layer 26 and thethreshold has not shifted is taken as the value “1.” The number ofcontrol gate electrode layers is taken to be four; the memorytransistors 35 used for writing and reading data (hereinbelow referredto as “selected cells”) are taken to be the memory transistors of thethird layer from the bottom having a silicon pillar connected to the bitline BL at the upper end portion of the silicon pillar. In other words,the control gate electrode CGb of the third layer from the bottom is thegate electrode of the selected cells.

(Writing Operation)

The writing of the data is performed in order simultaneously formultiple selected cells arranged in the X direction for one block at atime. Such multiple selected cells share the same control gate electrodeCG while belonging to mutually different memory strings 38 asillustrated in FIG. 1. Further, the multiple memory strings 38 of suchselected cells pierce a common selection gate electrode SG and areconnected to a common source line SL while being connected to mutuallydifferent bit lines BL.

First, the Y coordinate of the memory strings 38 (hereinbelow referredto as “selected strings”) of the memory transistors 35 to be written(the selected cells) is selected. Specifically, as illustrated in FIG.6, a selection gate potential V_(sg) is applied to the selection gateelectrode SGb of the selected strings; and an OFF potential V_(off) isapplied to the selection gate electrode SGs. The OFF potential V_(off)is applied to the selection gate electrodes SGb and SGs of theunselected memory strings 38. The OFF potential V_(off) is a potentialof the gate electrode of the transistor such that the transistor isswitched to the OFF state, e.g., a reference potential Vss. Thereference potential Vss is, for example, a grounding potential (0 V).The selection gate potential V_(sg) is a potential of the selection gateelectrode SG of the selection transistor 36 such that the conductingstate of the selection transistor 36 is determined by the potential ofthe silicon pillar (the body potential), e.g., a potential higher thanthe reference potential Vss. The potential of the back gate BG is takenas an ON potential V_(on). The ON potential V_(on) is a potential of thegate electrode of the transistor such that the transistor is switched tothe ON state, e.g., a power supply potential Vdd (e.g., 3.0 V).

Thereby, the selection transistors 36 on the bit line side of theselected strings are switched to the ON state and the OFF state by thepotential of the bit lines BL, and the selection transistors 36 on thesource line side are switched to the OFF state. All of the selectiontransistors 36 of the unselected memory strings 38 are switched to theOFF state. The back gate transistors 37 of all of the memory strings 38are switched to the ON state.

Then, the reference potential Vss (e.g., 0 V) is applied to the bitlines connected to the selected cells to be written with the value “0;”and the power supply potential Vdd (e.g., 3.0 V) is applied to the bitlines BL connected to the selected cells to be written with the value“1.” On the other hand, the power supply potential Vdd is applied to allof the source lines SL.

In this state, the positions of the selected cells of the selectedstrings are selected. Specifically, the potential of the control gateelectrodes CG of the selected cells, e.g., the control gate electrodesCGb of the third layer from the bottom, is increased to a writingpotential V_(pgm) (e.g., 18 V); and the potential of the other controlgate electrodes CG, i.e., the control gate electrodes CGb of the layersother than the third layer from the bottom and all of the control gateelectrodes CGs are provided with an intermediate potential V_(pass)(e.g., 10 V). At this time, because the control gate electrodes CGb ofthe third layer are connected to each other, the writing potentialV_(pgm) is applied to the control gate electrodes CGb of the third layeralso for the unselected memory strings. The writing potential V_(pgm) isa potential high enough to inject electrons from the silicon pillar 31into the charge storage layer 26 of the ONO film 24, and is a potentialhigher than the reference potential Vss and the selection gate potentialV_(sg). That is, Vss<V_(sg)<V_(pgm). Although the intermediate potentialV_(pass) is a potential higher than the reference potential Vss, theintermediate potential V_(pass) is a potential lower than the writingpotential V_(pgm). That is, Vss<V_(pass)<V_(pgm).

Thereby, for the selected cells to be written with the value “0,” thepotential difference between the source potential and the gate potentialof the selection transistors 36 on the bit line side exceeds thethreshold and the selection transistors 36 are switched to the ON statebecause the potential of the bit lines BL is the reference potential Vss(e.g., 0 V) and the potential of the selection gate electrodes SGb onthe bit line side is the selection gate potential V_(sg) higher than thereference potential Vss. As a result, the body potential V_(body) of theselected cells approaches the reference potential Vss. The potential ofthe control gate electrodes CG of the selected cells is the writingpotential V_(pgm) (e.g., 18 V). Accordingly, the difference(V_(pgm)−V_(body)) between the gate potential and the body potential ofthe selected cells is sufficiently large, high-temperature electrons arecreated by the potential difference, and the electrons are injected fromthe silicon pillar into the charge storage layer 26 via the tunnelinglayer 27. Thereby, the value “0” is written into the selected cells.

On the other hand, for the selected cells to be written with the value“1,” the potential of the bit lines BL is the positive potential Vdd(e.g., 3.0 V) and the potential of the selection gate electrodes SGb onthe bit line side is the selection gate potential V_(sg) higher than thereference potential Vss. Therefore, the potential difference between thesource potential and the gate potential of the selection transistors 36on the bit line side is small, and the selection transistors 36 areswitched to the OFF state by a back gate effect. Thereby, the siliconpillars 31 are in a floating state and the body potential V_(body) ofthe selected cells is maintained at a high value by coupling with thecontrol gate electrodes CG provided with the intermediate potentialV_(pass) (e.g., 10 V). Therefore, the difference (V_(pgm)−V_(body))between the writing potential V_(pgm) (e.g., 18 V) of the control gateelectrode CG of the selected cells and the body potential V_(body)decreases, and electrons are not injected into the charge storage layer26. As a result, the value “1” is written into the selected cells.

For the unselected memory strings 38, the potential of the siliconpillars 31 is in the floating state because the selection transistors 36at both of the end portions are switched to the OFF state. In such acase, the body potential V_(body) of the silicon pillars 31 can becontrolled by the potential applied to the control gate electrodes CG,the voltage increase rate thereof, and the potential of the selectiongate electrodes; and a high potential can be maintained. As a result,the difference (V_(pgm)−V_(body)) between the gate potential and thebody potential of the memory transistors 35 decreases, electrons are notinjected into the charge storage layer 26, and the initial value ismaintained.

Thus, in this embodiment, the writing row (the Y coordinate) is selectedby controlling the conducting state of the selection transistors, anddata is written to the memory strings 38 arranged in the X direction inorder by row. At this time, the potential of the control gate electrodesis controlled by block. Therefore, for the writing disturbance, it issufficient to consider the total time necessary for writing the data tothe memory strings in the block. Thereby, the disturbance time can becontrolled by adjusting the block size.

(Reading Operation)

As illustrated in FIG. 6, the ON potential V_(on) is applied to the backgate BG, and the back gate transistors 37 are switched to the ON state.The ON potential V_(on) (e.g., 3.0 V) is applied to the selection gateelectrodes SGs and SGb of the selected strings, and the selectiontransistors 36 are switched to the ON state. On the other hand, the OFFpotential V_(off) (e.g., 0 V) is applied to the selection gateelectrodes SGs and SGb of the unselected memory strings 38, and theselection transistors 36 are switched to the OFF state.

A potential is applied to the control gate electrode CG of the selectedcells, i.e., the control gate electrodes CGb of the third layer from thebottom, such that the value of the selected cells differs from theconducting state. The potential is, for example, the reference potentialVss (e.g., 0 V) and is a potential such that a current does not flow inthe body in the case where the value of the selected cell is “0,” i.e.,when electrons are stored in the charge storage layer 26 and thethreshold is shifted to positive and a current flows in the body in thecase where the value of the selected cell is “1,” i.e., when electronsare not stored in the charge storage layer 26 and the threshold is notshifted. For the memory transistors 35 other than those of the selectedcells, a reading potential V_(read) (e.g., 4.5 V) is applied to thecontrol gate electrodes thereof such that the memory transistors 35 areswitched to the ON state regardless of the value thereof.

In this state, a potential Vb1 (e.g., 0.7 V) is applied to each of thebit lines BL, and the reference potential Vss (e.g., 0 V) is applied toeach of the source lines SL. As a result, a current flows in theselected string if the value of the selected cell is “1” and a currentdoes not flow in the selected string if the value of the selected cellis “0.” Accordingly, the value of the selected cell can be read bydetecting the current flowing in the source line SL from the bit line BLvia the selected string or by detecting the potential drop of the bitline BL. For the unselected memory strings 38, a current does not flowregardless of the values stored in the memory transistors 35 because theselection transistors 36 are in the OFF state.

(Erasing Operation)

The unit of erasing data is by block.

As illustrated in FIG. 6, the ON potential V_(on) is applied to the backgate BG, and the back gate transistors 37 are switched to the ON state.The reference potential Vss (e.g., 0 V) is applied to all of the controlgate electrodes CG of the block to be erased (hereinbelow referred to as“selected block”). The potential of the bit lines BL and the sourcelines SL is increased to an erasing potential V_(erase) (e.g., 15 V).Also, the selection gate potential V_(sg) lower than the erasingpotential V_(erase) is applied to the selection gate electrodes SGb andSGs. That is, V_(sg)<V_(erase).

Thereby, the potential of the bit lines BL and the source lines SL isthe erasing potential V_(erase) (e.g., 15 V), and the potential of theselection gate electrodes SGb and SGs is the selection gate potentialV_(sg). Therefore, a Hall effect current is produced by tunnelingbetween bands due to the potential difference between the bit lines BLand the selection gate electrodes SGb and the potential differencebetween the source lines SL and the selection gate electrodes SGs; andthe potential of the silicon pillars 31, i.e., the body potential,increases. On the other hand, the reference potential Vss (e.g., 0 V) isapplied to the control gate electrodes CG of the block to be erased (theselected block). Therefore, holes are injected into the charge storagelayers 26 of the memory transistors 35 due to the potential differencebetween the silicon pillars 31 and the control gate electrodes CG, andelectrons in the charge storage layer 26 undergo pair annihilation. As aresult, the data is erased. Because the body potential increases due tothe injection of the Hall effect current, it is necessary to provide apotential difference between the erasing potential V_(erase) and theselection gate potential V_(sg) sufficient to inject sufficient holesinto the charge storage layer 26.

On the other hand, for the blocks not to be erased (the unselectedblocks), the potential of the selection gate electrodes SGb and SGs isincreased to a potential approaching the potential of the bit lines BLand the source lines SL, and the electric field between a diffusionlayer connected to the bit lines BL or the source lines SL and theselection gate electrodes SGb or SGs is weakened such that a Hall effectcurrent is not produced. Or, the potential of the control gateelectrodes CG is increased simultaneously with that of the siliconpillars 31 such that holes in the silicon pillars 31 are not injectedinto the charge storage layers 26. Thereby, the values already writtento the memory transistors 35 of the unselected blocks are maintainedas-is.

A method for manufacturing the nonvolatile semiconductor memory device 1according to this embodiment will now be described.

FIG. 7 to FIG. 15 are cross-sectional views of steps, illustrating themethod for manufacturing the nonvolatile semiconductor memory deviceaccording to this embodiment.

FIG. 7 to FIG. 15 illustrate the same cross section as FIG. 2.

First, as illustrated in FIG. 7, the silicon substrate 11 is prepared. Amemory cell formation region is set in the silicon substrate 11. Aperipheral circuit region (not illustrated) is set around the memorycell formation region. An element separation film is formed in aprescribed region of the upper layer portion of the silicon substrate11. At this time, the element separation film 59 (referring to FIG. 4)also is formed in a region where the dummy pillars 31 d (referring toFIG. 4) are formed in a subsequent step. Then, a thick film gateinsulating film for high breakdown voltage transistors and a thin filmgate insulating film for low breakdown voltage transistors are madeseparately in the peripheral circuit region. At this time, theinsulating film 10 is formed on the silicon substrate 11 also in thememory cell formation region.

Then, the polysilicon film 12 is deposited on the insulating film 10 asa conducting film with a thickness of, for example, 200 nm.Photolithography and RIE (Reactive Ion Etching) are performed on theupper layer portion of the polysilicon film 12 in the memory cellformation region to make multiple trenches 52 having rectangularconfigurations aligned in the Y direction on the upper face of thepolysilicon film 12. The trenches 52 are arranged in a matrixconfiguration along the X direction and the Y direction. The trenches 52are recesses made in the upper face of the polysilicon film 12.

Continuing as illustrated in FIG. 8, a silicon nitride film is depositedby, for example, CVD (Chemical Vapor Deposition) to form a sacrificialmember 53 on the polysilicon film 12. At this time, the sacrificialmember 53 also is filled into the trenches 52. Then, the sacrificialmember 53 and the polysilicon film 12 are patterned by, for example,photolithography and RIE. Thereby, the polysilicon film 12 in the memorycell formation region is divided for every block 50 (referring to FIG.4); back gates BG made of the polysilicon film 12 are formed inflat-plate configurations in each of the blocks 50; and gate electrodesmade of the polysilicon film 12 are formed in the peripheral circuitregion. Also at this time, the polysilicon film 12 is removed from theregion where the dummy pillars 31 d will be formed at the end portionsof each of the blocks 50.

Subsequently, a spacer made of silicon oxide is formed and a diffusionlayer is formed by ion implantation in the peripheral circuit region.Then, an inter-layer insulating film is deposited in the peripheralcircuit region, planarized, and recessed such that the upper facethereof is the same height as the upper face of the polysilicon film 12.Then, the sacrificial member 53 is recessed such that the sacrificialmember 53 is removed from the polysilicon film 12 and left only in theinteriors of the trenches 52.

Continuing as illustrated in FIG. 9, the insulating films 15 made of,for example, silicon oxide are deposited alternately with the electrodefilms 14 made of, for example, polysilicon on the back gate BG (thepolysilicon film 12) in the memory cell formation region to form thestacked body ML.

Then, as illustrated in FIG. 10, multiple through-holes 21 arecollectively made in the stacked body ML by, for example, RIE to alignin the Z direction. At this time, the through-holes 21 are arranged in amatrix configuration along the X direction and the Y direction. Thebottom portions of the through-holes 21 reach both end portions of thesacrificial member 53 filled into the trenches 52. Thereby, twothrough-holes 21 adjacent to each other in the Y direction reach thesacrificial member 53.

Continuing as illustrated in FIG. 11, wet etching is performed via thethrough-holes 21 to remove the sacrificial member 53 (referring to FIG.10) from the trenches 52. Thereby, the trench 52 becomes thecommunicating hole 22, and one continuous U-shaped hole 23 is formed ofthe communicating hole 22 and the two through-holes 21 communicatingwith both end portions thereof.

Then, as illustrated in FIG. 12, a silicon oxide film, a silicon nitridefilm, and a silicon oxide film are continuously deposited. Thereby, theblock layer 25 made of the silicon oxide film, the charge storage layer26 made of the silicon nitride film, and the tunneling layer 27 made ofthe silicon oxide film are stacked in this order on the inner face ofthe U-shaped hole 23 to form the ONO film 24.

Then, amorphous silicon is deposited on the entire surface. Thereby,amorphous silicon is filled into the U-shaped hole 23 to form theU-shaped silicon member 33. The U-shaped silicon member 33 is formedfrom the pair of silicon pillars 31 filled into the through-holes 21 andthe one connection member 32 filled into the communicating hole 22.Subsequently, the amorphous silicon, the silicon oxide film, the siliconnitride film, and the silicon oxide film deposited on the stacked bodyML are removed.

Continuing as illustrated in FIG. 13, the stacked body ML is patternedby, for example, RIE to make trenches 54 in the stacked body ML. Thetrench 54 is made to align in the X direction to link the regionsbetween the two silicon pillars 31 connected to the connection member 32and reach the insulating film 15 of the lowermost layer.

At this time, as illustrated in FIG. 4 and FIG. 5, the trenches 54 aremade to divide the electrode films 14 into a pair of mutually meshedcomb-shaped patterns. In other words, the trenches 54 are made in thecentral portion of the stacked body ML in the X direction to align inthe X direction. Thereby, the electrode films 14 are divided intomultiple control gate electrodes CG aligned in the X direction. At thistime, the trenches 54 are not made in the regions directly above theregions between the connection members 32 in the Y direction. Thereby,each of the control gate electrodes CG is pierced by two of the siliconpillars 31 arranged along the Y direction. At both X-direction endportions of the stacked body ML, the trenches 54 are not aligned in theX direction and are made to align intermittently in the Y direction.Thereby, the control gate electrodes CGb and CGs alternately disposedalong the Y direction at the central portion of the stacked body ML inthe X direction have common connections to each other at each of theX-direction end portions of the stacked body ML.

Then, as illustrated in FIG. 14, the insulating film 16 is deposited onthe stacked body ML and planarized. The insulating film 16 also isfilled into the trenches 54. Then, the conducting film 17 made of, forexample, amorphous silicon is deposited, etched, and left only in thememory cell region.

Then, a resist film (not illustrated) is formed, for example, on theconducting film 17, and the stacked body ML is patterned into astairstep configuration by repeatedly performing etching using theresist film as a mask and performing slimming of the resist film.Thereby, both X-direction end portions of the control gate electrodes CGfor each level are not covered with the control gate electrodes CG ofthe level thereabove as viewed from above (the Z direction); and insubsequent steps, contacts can be formed from above to each level of thecontrol gate electrodes CG. Then, an etching stopper film (notillustrated) made of, for example, silicon nitride is formed to coverthe stacked body ML patterned into the stairstep configuration; aninter-layer insulating film (not illustrated) is formed thereupon; andthe upper face is planarized. Thereby, the inter-layer insulating filmis filled around the stacked body ML.

Subsequently, the insulating film 18 is formed on the conducting film17. The through-holes 51 are made to pierce the insulating film 18, theconducting film 17, and the insulating film 16 to reach the upper endsof the through-holes 21 in the stacked body ML.

Then, as illustrated in FIG. 15, an insulating film is deposited on theentire surface, and amorphous silicon is deposited. Etch-back isperformed on the amorphous silicon and the insulating film to leave theamorphous silicon and the insulating film only in the through-holes 51.Thereby, the gate insulating film 28 is formed on the inner face of thethrough-holes 51 and the amorphous silicon is filled. Then, heattreatment is performed at a temperature of, for example, 600° C. tocrystallize the amorphous silicon in the through-holes 51 to formpolysilicon. Ion implantation is performed on the polysilicon usingarsenic (As) with, for example, an acceleration voltage of 40 keV and adose of 3×10¹⁵ cm⁻² to form a drain diffusion layer (not illustrated).Thereby, the silicon pillars 34 are formed in the through-holes 51. Thesilicon pillars 34 connect to the silicon pillars 31.

Continuing, patterning by RIE and the like is performed on theinsulating film 18 and the conducting film 17 to make trenches 55aligned in the X direction in the regions between the silicon pillars 34adjacent to each other in the Y direction. Thereby, the conducting film17 is divided along the Y direction to form multiple selection gateelectrodes SG aligned in the X direction.

Then, as illustrated in FIG. 2, the insulating film 19 is formed on theinsulating film 18, source plugs SP are buried in the insulating film19, and the source lines SL are formed on the insulating film 19 toalign in the X direction. At this time, the source lines SL areconnected to the drain diffusion layers of some of the silicon pillars34 via the source plugs SP. Contacts (not illustrated) are formed in theinter-layer insulating film (not illustrated) provided around thestacked body ML to connect to each of the control gate electrodes CG andeach of the selection gate electrodes SG from above. Then, theinsulating film 20 is formed on the insulating film 19 to cover thesource lines SL. Then, the bit plugs BP are buried in the insulatingfilms 20 and 19 and the bit lines BL are formed on the insulating film20 to align in the Y direction. At this time, the bit lines BL areconnected to the drain diffusion layers of the remaining silicon pillars34 via the bit plugs BP. Thereby, the nonvolatile semiconductor memorydevice 1 is manufactured.

Effects of this embodiment will now be described.

In this embodiment, the U-shaped silicon member 33 is formed integrallywithout breaks by filling polysilicon into the interior of the U-shapedhole 23. Therefore, unlike the stacked memory device discussed in, forexample, JP-A 2007-266143(Kokai), contacts are unnecessary between thesilicon of the lower portions of the through-holes 21. Accordingly, itis unnecessary to perform pre-processing such as hydrofluoric acidprocessing to remove native oxide films and the like from the surface ofsilicon members formed beforehand, and the charge storage layer is notdamaged by such pre-processing. As a result, a nonvolatile semiconductormemory device can be realized having good memory transistorcharacteristics.

Also, according to this embodiment, unlike the stacked memory devicediscussed in Patent Literature 1, the source lines can be formed asmetal interconnects disposed above the stacked body ML instead ofdiffusion layers formed in the silicon substrate. Thereby, theresistance of the source lines can be reduced, and data can be easilyread. The impurity concentration of the silicon pillars does notundesirably increase as in the case where the source lines are formed ofdiffusion layers, impurities of the diffusion layers desorb into avapor, and the impurities re-adhere during the depositing of the siliconpillars. Therefore, the cut-off characteristics of the transistor do notdecline as in the case where the impurity concentration of the siliconpillars increases. Moreover, by disposing the source lines on thestacked body ML, the vias for connecting to the source lines can be madeshallow, and the vias can be easily constructed. Thereby, fine vias canbe made, and therefore one source line can be formed for each of twoseries of silicon pillars arranged along the X direction.

Further, according to this embodiment, the selection gate electrodes SGson the source line side also can be disposed above the stacked body MLby forming the memory strings in U-shaped configurations and disposingthe source lines above the stacked body ML. Thereby, the vias forconnecting the upper layer interconnects to the selection gateelectrodes SGs can be short, and a low aspect ratio can be maintainedfor finer vias. As a result, the selection gate electrodes SGs on thesource line side can be divided every silicon pillar and drivenindependently from each other similarly to the selection gate electrodesSGb on the bit line side. Thereby, the degrees of freedom of theoperations of the device 1 increase. For example, only the siliconpillars of the selected strings during a reading operation may beconnected to the source lines SL instead of those of all of the memorystrings; and thereby, the disturbance time during the reading can bereduced.

Also, according to this embodiment, each of the control gate electrodesCG are pierced by two silicon pillars 31 adjacent to each other in the Ydirection; and two silicon pillars 31 connected to each other by theconnection member 32 pierce mutually different control gate electrodesCG. Thereby, it is possible to store data in the memory transistors 35of each of the memory strings 38 mutually independently, while the widthof the control gate electrodes CG in the Y direction can be larger thanthe arrangement period of the silicon pillars 31. As a result, whenmaking the trenches 54 in the stacked body ML during the stepillustrated in FIG. 13, it is sufficient to make one trench 54 for everytwo silicon pillars 31. Thereby, the width of each portion of thestacked body ML divided by the trenches 54 can be increased. As aresult, it is possible to prevent the collapse of such portions duringthe step illustrated in FIG. 13.

Such effects will now be described more specifically with reference to acomparative example.

FIGS. 16A and 16B are cross-sectional views of steps, illustratingportions of a stacked body divided in the step illustrated in FIG. 13.FIG. 16A illustrates the comparative example. FIG. 16B illustrates thisembodiment.

In a device 101 according to the comparative example of this embodimentillustrated in FIG. 16A, the trenches 54 are made in all of the regionsbetween the silicon pillars 31 arranged along the Y direction. In such acase, although all of the memory transistors of each of the memorystrings 38 can be controlled independently because the control gateelectrodes are formed for every series made of the silicon pillars 31arranged in the X direction, in each portion 58 of the stacked body MLdivided by the trenches 54, the width in the Y direction is undesirablyexceedingly narrow. Therefore, there is a possibility that the portions58 may collapse partway through the step or the control gate electrodesCG formed in adjacent portions 58 may undesirably contact each other.

Conversely, according to the device 1 according to this embodimentillustrated in FIG. 16B, the trenches 54 are made in every other regionbetween the silicon pillars 31 arranged along the Y direction. Thereby,the trenches 54 are not made in the remaining every other region, andtherefore the width of the portions 58 divided by the trenches 54 can bewidened. In one example, in the case where twenty-four stacks of thecontrol gate electrodes CG are used, the aspect ratio of the portion 58in the YZ plane is 5.6 for this embodiment, which is less than half of13.7 for the comparate example. Thereby, the possibility that theportions 58 may collapse can be drastically reduced. Also, by making thetrenches 54 between the two silicon pillars 31 connected to each otherby the connection member 32, these silicon pillars 31 can piercemutually different control gate electrodes CG. Thereby, all of thememory transistors of each of the memory strings 38 can be provided withmutually different control gate electrodes, and the memory transistorscan be independently controlled.

As illustrated in FIG. 5, in this embodiment, the device 1 is dividedinto multiple blocks 50, and the control gate electrodes CG areelectrically separated between the blocks. Thereby, independentpotentials can be applied to the control gate electrodes for each of theblocks, and data can be written and erased by block. In this embodiment,the dummy silicon pillars (dummy pillars) 31 d are provided at theY-direction end portions of the blocks 50. Thereby, the through-holes 21can be made while maintaining periodicity at the end portions of theblocks 50 as well, and the lithography for making the through-holes 21is easier.

Although the chip surface area increases somewhat by providing the dummypillars and by disposing the dummy pillars only at the end portions ofthe blocks as described above, a large increase of the surface area canbe suppressed. In one example, in the case where twenty-four stacks ofthe control gate electrode CG are used, the increase of the surface areadue to providing the dummy pillars can be suppressed to 7.69%.

Further, in each of the blocks, the multiple memory transistors arrangedin the X direction share control gate electrodes, and the control gateelectrodes have common connections to each other. Thereby, the controlgate electrodes of each of the levels are collected into the two controlgate electrodes CGs and CGb. Thereby, the driver circuit for driving thecontrol gate electrodes can be shared. As a result, it is unnecessary toincrease the number of drive circuits proportionally to the increase ofthe number of bits per unit surface area, and the increase of thesurface area due to increasing driver circuits can be suppressed.

A second embodiment of the invention will now be described.

FIG. 17 is a cross-sectional view illustrating a nonvolatilesemiconductor memory device according to this embodiment.

FIG. 18 is a plan view illustrating the nonvolatile semiconductor memorydevice according to this embodiment.

For easier viewing of the drawings, only the silicon substrate and theelectrically conducting portions are illustrated in FIG. 17 and FIG. 18,and the insulating portions are omitted. In particular, FIG. 18illustrates only the silicon substrate, the back gates, the control gateelectrodes, and the U-shaped silicon members.

As illustrated in FIG. 17 and FIG. 18, a nonvolatile semiconductormemory device 2 according to this embodiment includes dummy control gateelectrodes CGd disposed between two adjacent blocks 50 and connected tonone of the control gate electrodes CGs and the control gate electrodesCGb. The dummy control gate electrodes CGd (hereinbelow also referred toas “dummy gate electrodes”) have line configurations aligned in the Xdirection and are in, for example, an electrically floating state.

The portions of the control gate electrodes CGs aligned in the Xdirection in each of the blocks 50 (the comb teeth portions), theportions of the control gate electrodes CGb aligned in the X directionin each of the blocks 50, and the dummy gate electrodes CGd disposedbetween the blocks 50 are arranged with uniform spacing along the Ydirection such that the control gate electrode CGb, the dummy gateelectrodes CGd, and the control gate electrode CGb are arranged in thisorder along the Y direction in and around the region between the blocks50.

Similarly to the control gate electrodes CGs and CGb, the dummy gateelectrodes CGd also are pierced by two series of silicon pillars 31arranged along the X direction. The silicon pillars 31 piercing thedummy gate electrodes CGd are connected to the source line SL disposedin the region directly thereabove. Each of these silicon pillars 31 isconnected by the connection member 32 to a silicon pillar 31 piercingthe control gate electrodes CGb disposed adjacent to the dummy gateelectrodes CGd to form one U-shaped pillar 30 d. The U-shaped pillar 30d is a dummy U-shaped pillar that does not contribute to storing data.

The back gates BG are provided in the regions directly below the blocks50 and the region between the blocks 50. In other words, although theback gates BG are provided in the regions directly below the normalU-shaped pillars 30 and the dummy U-shaped pillars 30 d, the back gatesBG are not provided in the regions directly below the dummy siliconpillars 31 d. The element separation film 59 is formed in the region ofthe silicon substrate 11 between the blocks 50. Otherwise, theconfiguration, operations, and manufacturing method of this embodimentare similar to those of the first embodiment described above.

The effects of this embodiment will now be described.

According to this embodiment, the periodicity of the arrangement of thebit plugs BP for connecting the bit lines BL to the silicon pillars 34can be kept constant also for the boundary portion between the blocks50. In other words, an arrangement pattern in which two bit plugs BP arealternately arranged with two source plugs SP along the Y direction canbe continuously realized both in the interior of the blocks 50 and inthe regions between the blocks 50. Thereby, the lithography margin forforming the bit plugs BP can be easily ensured. Otherwise, the effectsof this embodiment are similar to those of the first embodimentdescribed above.

Although an example is illustrated in this embodiment where the dummygate electrodes CGd are in a floating state, the dummy gate electrodesCGd may be driven independently from the control gate electrodes CGs andCGb. Thereby, it is possible to store data also in the U-shaped pillars30 d.

A modification of this embodiment will now be described.

FIG. 19 is a cross-sectional view illustrating a nonvolatilesemiconductor memory device according to this modification.

FIG. 20 is a plan view illustrating the nonvolatile semiconductor memorydevice according to this modification.

For easier viewing of the drawings, only the silicon substrate and theelectrically conducting portions are illustrated in FIG. 19 and FIG. 20,and the insulating portions are omitted. In particular, FIG. 20illustrates only the silicon substrate, the back gates, the control gateelectrodes, and the U-shaped silicon members.

As illustrated in FIG. 19 and FIG. 20, the disposition of the controlgate electrodes in the blocks 50 in a nonvolatile semiconductor memorydevice 2 a according to this modification differs from that of thenonvolatile semiconductor memory device 2 (referring to FIG. 17 and FIG.18) according to the second embodiment described above. In other words,in this modification, the control gate electrodes CGb, the dummy gateelectrodes CGd, and the control gate electrodes CGs are arranged in thisorder along the Y direction in and around the region between the blocks50. Otherwise, the configuration, operations, manufacturing method, andeffects of this modification are similar to those of the secondembodiment described above.

A third embodiment of the invention will now be described.

FIG. 21 is a cross-sectional view illustrating a nonvolatilesemiconductor memory device according to this embodiment.

FIG. 22 is a plan view illustrating the nonvolatile semiconductor memorydevice according to this embodiment.

For easier viewing of the drawings, only the silicon substrate and theelectrically conducting portions are illustrated in FIG. 21 and FIG. 22,and the insulating portions are omitted. In particular, FIG. 22illustrates only the silicon substrate, the back gates, the control gateelectrodes, and the U-shaped silicon members.

As illustrated in FIG. 21 and FIG. 22, a nonvolatile semiconductormemory device 3 according to this embodiment differs from thenonvolatile semiconductor memory device 2 a (referring to FIG. 19 andFIG. 20) according to the modification of the second embodimentdescribed above in that the dummy gate electrodes CGd are narrow, andthe silicon pillars 31 piercing the dummy gate electrodes CGd arearranged in one series along the X direction. The control gateelectrodes CGs, the dummy gate electrodes CGd, and the control gateelectrodes CGs are arranged in this order along the Y direction in andaround the region between the blocks 50.

A source line SLw having a width wider than that of other source linesSL is provided in the region directly above the one silicon pillar 31piercing the dummy gate electrode CGd and the two silicon pillars 31piercing the one control gate electrode CGs disposed on one Y directionside of the dummy gate electrode CGd. The upper end portions of thesethree silicon pillars 31 have a common connection to the source lineSLw. That is, three series of the silicon pillars 31 are connected tothe source line SLw.

A connection member 32 w having a Y direction length longer than that ofthe other connection members 32 is provided in the region directly belowthe one silicon pillar 31 piercing the dummy gate electrode CGd and thetwo silicon pillars 31 disposed one on each side of the one siliconpillar 31 in the Y direction. The lower end portions of these threesilicon pillars 31 have a common connection to the connection member 32w. That is, three series of silicon pillars 31 are connected to theconnection member 32 w.

The dummy gate electrodes CGd are insulated from the control gateelectrodes CGs and CGb and are in, for example, a floating state.Therefore, the silicon pillar 31 d piercing the dummy gate electrodesCGd is connected between the source line SLw and the connection member32 w but does not contribute to storing data and is a dummy pillar. Thetwo silicon pillars 31 disposed one on each of the Y direction sides ofthe silicon pillar 31 piercing the dummy gate electrodes CGd areconnected to each other via the connection member 32 w. Otherwise, theconfiguration, operations, and manufacturing method of this embodimentare similar to those of the modification of the second embodimentdescribed above.

The effects of this embodiment will now be described.

Comparing to the second embodiment and the modification of the secondembodiment described above, the chip surface area can be reducedaccording to this embodiment because the dummy pillars are disposed inone series in the region between the blocks 50. Although the portion ofthe divided stacked body ML including the dummy gate electrodes CGd hasa narrower width and there is an increased possibility of collapse onlyfor this portion, the widths of the other portions are the width of twoseries of silicon pillars, and the possibility of collapsing is low.Also, the number of the portions including the dummy gate electrodes CGdis lower than the number of the portions including the control gateelectrodes CGs and the control gate electrodes CGb. Therefore, as anentirety, the possibility that discrepancies may occur in the device 3due to the collapse of the divided portions does not increase very much.Otherwise, the effects of this embodiment are similar to those of thefirst embodiment described above.

Hereinabove, the invention is described with reference to exemplaryembodiments. However, the invention is not limited to these embodiments.For example, additions, deletions, or design modifications of componentsor additions, omissions, or condition modifications of stepsappropriately made by one skilled in the art in regard to theembodiments described above are within the scope of the invention to theextent that the purport of the invention is included. For example,although a description of the peripheral circuit is omitted in theembodiments described above, various circuits are provided in actualnonvolatile semiconductor memory devices to drive the memory strings andthe like. Also, although a description of process films such as etchingstopper films, diffusion prevention films, etc., are omitted in theembodiments described above, such process films may be appropriatelyformed according to the necessity of the process. Further, planarizingsteps, cleaning steps, etc., may be appropriately provided between thesteps described above.

1. A nonvolatile semiconductor memory device, comprising: a stacked bodyincluding a plurality of insulating films alternately stacked with aplurality of electrode films, the electrode films being divided to forma plurality of control gate electrodes aligned in a first direction; aplurality of selection gate electrodes provided on the stacked body andaligned in the first direction; a plurality of semiconductor pillarsaligned in a stacking direction of the stacked body, the semiconductorpillars being arranged in a matrix configuration along the firstdirection and a second direction intersecting the first direction topierce the control gate electrodes and the selection gate electrodes; aplurality of source lines aligned in the first direction and connectedto upper end portions of some of the semiconductor pillars; a pluralityof bit lines aligned in the second direction and connected to upper endportions of a remainder of the semiconductor pillars; a connectionmember connecting a lower end portion of one of the semiconductorpillars to a lower end portion of one other of the semiconductorpillars, an upper end portion of the one of the semiconductor pillarsbeing connected to the source line, an upper end portion of the oneother of the semiconductor pillars being connected to the bit line; acharge storage layer provided between one of the control gate electrodeand one of the semiconductor pillar; and a gate insulating film providedbetween one of the selection gate electrode and one of the semiconductorpillar, at least some of the control gate electrodes being pierced bytwo of the semiconductor pillars adjacent to each other in the seconddirection, two of the semiconductor pillars being connected to eachother by the connection member and provided to pierce mutually differentcontrol gate electrodes.
 2. The device according to claim 1, wherein thecontrol gate electrodes are organized into a plurality of blocks setalong the second direction, the control gate electrodes of each of theblocks are further organized into two groups, the control gateelectrodes of one group are alternately arranged along the seconddirection with the control gate electrodes of another group in each ofthe blocks, the control gate electrodes of each of the groups have acommon connection for the group, and a lower end portion of thesemiconductor pillar disposed at an end portion in the second-directionof each of the blocks is not connected to the connection member.
 3. Thedevice according to claim 2, further comprising: a substrate; and a backgate provided between the substrate and the stacked body, the connectionmember being disposed in an interior of the back gate, the back gate notbeing provided in a region directly below a semiconductor pillar notconnected to the connection member.
 4. The device according to claim 2,wherein the electrode films of each of the blocks are subdivided into apair of mutually meshed comb-shaped patterns.
 5. The device according toclaim 2, wherein a control gate electrode is disposed between the twoadjacent blocks and connected to none of the control gate electrodes ofthe one group and the control gate electrodes of the another group ofeach of the two blocks.
 6. The device according to claim 5, wherein aconfiguration of the control gate electrode connected to none is a lineconfiguration aligned in the first direction.
 7. The device according toclaim 5, wherein the control gate electrode connected to none is in afloating state.
 8. The device according to claim 5, wherein the controlgate electrodes of the one group, the control gate electrode connectedto none, and the control gate electrodes of the another group arearranged with uniform spacing along the second direction.
 9. The deviceaccording to claim 5, wherein the control gate electrode connected tonone is pierced by two of the semiconductor pillars, the two of thesemiconductor pillars being adjacent in the second direction andconnected to a common one of the source lines, and another two of thesemiconductor pillars on each adjacent side in the second direction ofthe two of the semiconductor pillars piercing the control gate electrodeconnected to none are connected to one of the bit lines.
 10. The deviceaccording to claim 5, wherein the control gate electrode connected tonone is pierced by two of the semiconductor pillars, the two of thesemiconductor pillars being adjacent in the second direction andconnected to a common one of the source lines, and as viewed from thetwo of the semiconductor pillars, another two of the semiconductorpillars disposed on one side adjacent in the second direction areconnected to one of the bit lines and still another two of thesemiconductor pillars disposed on another side adjacent in the seconddirection are connected to one of the source lines.
 11. The deviceaccording to claim 5, wherein the control gate electrode connected tonone is pierced by one series of dummy semiconductor pillars arrangedalong the first direction, the dummy semiconductor pillars are connectedto the connection member connected to two of the semiconductor pillarsdisposed on each side of the dummy semiconductor pillars, and the two ofthe semiconductor pillars are connected to the source lines.
 12. Thedevice according to claim 11, wherein the dummy semiconductor pillarsare connected to one of the source lines connected to one of the two ofthe semiconductor pillars.
 13. The device according to claim 12, whereina width of the one of the source lines connected to the dummysemiconductor pillars is wider than a width of another one of the sourcelines.
 14. The device according to claim 1, further comprising: asubstrate; and a back gate provided between the substrate and thestacked body, the connection member being disposed in an interior of theback gate.
 15. A method for manufacturing a nonvolatile semiconductormemory device, comprising: forming a conducting film on a substrate;making a plurality of recesses in an upper face of the conducting film,the recesses being arranged in a matrix configuration along a firstdirection and a second direction intersecting the first direction;filling sacrificial members into the recesses; forming a stacked body onthe conducting film, the stacked body including a plurality ofinsulating films alternately stacked with a plurality of electrodefilms; making through-holes in the stacked body, the through-holes beingaligned in a stacking direction of the stacked body and provided in amatrix configuration along the first direction and the second direction,two of the through-holes adjacent in the second direction reaching eachof the sacrificial members; performing etching via the through-holes toremove the sacrificial members; forming a charge storage layer on innerfaces of the through-holes and the recesses; filling a semiconductormaterial into interiors of the through-holes and the recesses to form aconnection member in the recesses and semiconductor pillars in thethrough-holes; making a trench in the stacked body to divide theelectrode films into a plurality of control gate electrodes aligned inthe first direction, the trench being aligned in the first direction tolink regions between two of the semiconductor pillars connected to eachother by the connection member, the control gate electrodes beingpierced by two of the semiconductor pillars arranged along the seconddirection; forming another conducting film on the stacked body; makingother through-holes in the another conducting film in regions directlyabove the through-holes; forming a gate insulating film on inner facesof the other through-holes; filling a semiconductor material intointeriors of the other through-holes to form other semiconductor pillarsconnected to the semiconductor pillars; dividing the another conductingfilm to form a plurality of selection gate electrodes aligned in thefirst direction; forming a plurality of source lines aligned in thefirst direction and connected to upper end portions of some of the othersemiconductor pillars; and forming a plurality of bit lines aligned inthe second direction and connected to upper end portions of remainder ofthe other semiconductor pillars.
 16. The method according to claim 15,further comprising: removing the conducting film from an end portion inthe second-direction of each of a plurality of blocks set along thesecond direction, the dividing into the plurality of the control gateelectrodes including organizing the control gate electrodes into theplurality of the blocks, further organizing the control gate electrodesof each of the blocks into two groups, arranging the control gateelectrodes of one group alternately with the control gate electrodes ofanother group along the second direction in each of the blocks, andproviding the control gate electrodes of each of the groups with acommon connection for the group.
 17. The method according to claim 16,wherein the dividing into the plurality of the control gate electrodesincludes forming a control gate electrode between two of the adjacentblocks, the control gate electrode being connected to none of thecontrol gate electrodes of the one group and the control gate electrodesof the another group of each of the two blocks.